Sleeping DDR3 controler

Hi,

i am using the DDR3 uniphy controler (QII V13.1) on a Stratix4GX 530 (evaluation board from Altera) and i am a little bit surprised that after a short period of high activity then signal "avl_ready" is deasserted for a few (4 to 6) µs though there is absolutely no activity on memory bus!

this is not very convenient to achieve performances goals.

Is this a normal behavior or do i miss something on the IP configuration?

Thanks to anyone abble to answer.

Jean Rene