Single Clock vs Multiple Clock, which approach is the best ?

Hi,

Advantages of using PLL inside FPGA:

1) Lesser FPGA pins are required.

2) With PLL generated clocks, you can control the phase relationship with incoming clock as well as other generated clocks.

3) Wide range of frequencies can be generated and can also be changed anytime.

4) Board space is saved.

Disadvantage of PLL:

Compared to the advantages there are very less disadvantage.

1) Introduction of a small amount of jitter, but this is application specific requirement.

2) The FPGA PLLs usually work on high frequency inputs, ~5MHz or more. It cannot be used for slower clocks. Check individual device datasheet for that.

I would prefer one clock input and generated the others as required. This way, there is more control with FPGA designer and less burden on board designers.

Regards