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Altera_Forum's avatar
Altera_Forum
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13 years ago

Sine wave simulation

I have a code for generating sine wave in VHDL. But i dont know how to simulate it. Any DAC simulator available ....????pls help me...its urgent

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    In what form is the output? std_logic_vector?

    In modelsim you can change the representation of the signal into "analog". The simulator then draws the sine wave if the design is correct.