Simulation problem with simple edge detector

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other options include:

1) generate data on clocked process anf forget about specific after figures. Or

2) register your comb statement on the clk edge

I normally use option 1

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This is where you can start building up your testbench_tools_pkg with stuff like this:

procedure wait_for_clks(signal clk : in std_logic; n : natural) is
begin
  for i in 1 to n loop  --loop 1 to n to allow 0 to  wait for 0 clocks
    wait until rising_edge(clk);
  end loop;
end procedure wait_for_clks;
    
......
process
begin
  input <= a;
  wait_for_clks(clk, 10);
  input <= b;
  wait_for_clks(some_other_clk, 100);
  input <= c;
  wait;
end process;