Honored Contributor
Honored ContributorI share your frustration, David. This forum is a ghost town compared to the Xilinx user forum. I don't know if that's due more to lack of attention from Altera or just a general lack of customers actively working on Altera designs. We are also targeting Arria 10, in our case the Arria 10 SoC. We started in a Xilinx Zynq but ran into some limitations that made us take another look at Arria 10. The silicon looks great, but the Altera tools, the number of dev kits and reference designs to work with, the forum support, and the documentation are all way behind Xilinx. It's not even close. Altera better step it up or they will never ever be competetive with Xilinx again.
Sorry I can't help you with your problem, but I couldn't pass up an opportunity to vent a little. There could very well be a problem with the fPLL simulation model. You might try doing a gate-level simulation and see if it behaves any differently. Or if you have a dev kit available try it in the hardware and make sure it works there. Good luck. Bob
