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Altera_Forum
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10 years ago

Simulation of ARRIA 10 FPLL & IOPLL phase shift

I am building a RGMII interface using the following IP blocks and some custom logic. 1) Altera GPIO (setup as DDIO output with data width = 5 for data[3:0] & CTL). 2) Altera GPIO (setup as DDIO ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hello, hello, hello....

Is there anybody in there?

Just nod if you can hear me.

Is there anyone at home?