Forum Discussion
simulation error occuring
the program i have given below applies a multiplication block using a paakage ..i m having problem when i generate a waveform for given inputs its not multiplying it the error is probably due to res:= res_lcl(vector length ) can any one debug this.
the project is modelling of fir filter using general equation of fir addition package library ieee; use ieee.std_logic_1164.all; package add_std is function "+" (A,B : in std_logic_vector) return std_logic_vector; end add_std; package body add_std is function "+" (A,B : in std_logic_vector) return std_logic_vector is variable C: std_logic_vector(A'length - 1 downto 0); variable D: std_logic_vector(A'length downto 0); begin D(0):= '0'; C:= (A xor B) xor D(A'length - 1 downto 0); D(A'length downto 1):= (A and B) or (A and D(A'length - 1 downto 0)) or (D(A'length - 1 downto 0) and B); return C; end "+"; end add_std; multiplication block library ieee; use ieee.std_logic_1164.all; use work.add_std.all; entity mult is port(br, qr : in std_logic_vector(3 downto 0); res : out std_logic_vector(6 downto 0)); end mult; architecture beh of mult is begin process(br,qr) variable br_bar : std_logic_vector(3 downto 0); variable res_lcl : std_logic_vector(8 downto 0); begin br_bar := not br; res_lcl := "0000" & qr & '0'; for i in 0 to 3 loop case res_lcl(1 downto 0) is when "00" => res_lcl(7 downto 0):= res_lcl(8 downto 1); when "01" => res_lcl(8 downto 5):= res_lcl(8 downto 5) + br; res_lcl(7 downto 0):= res_lcl(8 downto 1); when "10" => res_lcl(8 downto 5):= res_lcl(8 downto 5) + br_bar + "0001"; res_lcl(7 downto 0):= res_lcl(8 downto 1); when "11" => res_lcl(7 downto 0):= res_lcl(8 downto 1); when others => res_lcl:= res_lcl; end case; end loop; res<= res_lcl(7 downto 1); end process; end beh;2 Replies
- Altera_Forum
Honored Contributor
I think you are overcomplicating things by creating your own "+" function. The synthsisor and simulator are optimised for using the ieee.numeric_std package (or if you really have to, the ieee.std_logic_arith/std_logic_unsigned packages). These already provide as many +, *, resiziing and anything else you could ever think of. They are also great for the synthesiser to infer hardware adders and multipliers from. Custom functions may not have hardware infered from them.
- Altera_Forum
Honored Contributor
Your code is too verbose and I believe you are not doing it the easy way.
just use altera multipliers and adders. If you have say 16 taps, you design a delay line for 16 input stages. Then use 16 altera multiplier(megawizard or inference) to multiply each stage by a coefficient, then add up all results in succession : add up first 8 pairs of results then add up the resulting 4 pairs then the 2 pairs and the last pair(inserting pipeline registers at adder result) then truncate the final sum. use altera adder(not xor). You can truncate after each multiplier result or anywhere you wish till the final sum... If your coefficients are symmetrical you may use half multipliers by adding two corresponding input stages first then multiply.