Altera_Forum
Honored Contributor
17 years agosimulation error occuring
the program i have given below applies a multiplication block using a paakage ..i m having problem when i generate a waveform for given inputs its not multiplying it the error is probably due to res:= res_lcl(vector length ) can any one debug this.
the project is modelling of fir filter using general equation of fir addition package library ieee; use ieee.std_logic_1164.all; package add_std is function "+" (A,B : in std_logic_vector) return std_logic_vector; end add_std; package body add_std is function "+" (A,B : in std_logic_vector) return std_logic_vector is variable C: std_logic_vector(A'length - 1 downto 0); variable D: std_logic_vector(A'length downto 0); begin D(0):= '0'; C:= (A xor B) xor D(A'length - 1 downto 0); D(A'length downto 1):= (A and B) or (A and D(A'length - 1 downto 0)) or (D(A'length - 1 downto 0) and B); return C; end "+"; end add_std; multiplication block library ieee; use ieee.std_logic_1164.all; use work.add_std.all; entity mult is port(br, qr : in std_logic_vector(3 downto 0); res : out std_logic_vector(6 downto 0)); end mult; architecture beh of mult is begin process(br,qr) variable br_bar : std_logic_vector(3 downto 0); variable res_lcl : std_logic_vector(8 downto 0); begin br_bar := not br; res_lcl := "0000" & qr & '0'; for i in 0 to 3 loop case res_lcl(1 downto 0) is when "00" => res_lcl(7 downto 0):= res_lcl(8 downto 1); when "01" => res_lcl(8 downto 5):= res_lcl(8 downto 5) + br; res_lcl(7 downto 0):= res_lcl(8 downto 1); when "10" => res_lcl(8 downto 5):= res_lcl(8 downto 5) + br_bar + "0001"; res_lcl(7 downto 0):= res_lcl(8 downto 1); when "11" => res_lcl(7 downto 0):= res_lcl(8 downto 1); when others => res_lcl:= res_lcl; end case; end loop; res<= res_lcl(7 downto 1); end process; end beh;