Forum Discussion

New Contributor

1 year ago

Simulating F2H ACE-LITE interface on HPS.

Hello, I am finding that F2H ACE-lite interface in HPS IP have no implementation in simulation model. All outputs on this interface not driven by HPS, and after tracing in to HPS i found that nothi...

Configuration

aikeu

Regular Contributor

1 year ago

Hi awaissman,

I found this old design example as below as reference, hope it helps:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/exm-hps-axi-bfm.html

Thanks.

Regards,

Aik Eu

Forum Discussion

Simulating F2H ACE-LITE interface on HPS.

Recent Discussions

MAX 10 PLL Inverted Output Timing Inquiry

Error (209014): CONF_DONE pin failed to go high in device 1.

Agilex 3: VCCBAT pin for the battery-backed key storage.

Regarding the Footprint creation of AGFB022R24C2E2V

Dedicated Clock Pins for MAX 10