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Altera_Forum's avatar
Altera_Forum
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14 years ago

Simple Verilog Question--Impossible?

I have a verilog file Intensifier.v. In it is a module with the following port list: module Intensifier ( clk, _reset, intensifierInput, intensifierOutpu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

DEAR,

Thanks man!

I tried your code and it's ok.

But i don't know why when i didn't use "signed" to declare signals, it also is ok,however in >+500 and 0-500.

Anyway, thanks for your care!

Best regards!