Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Simple Verilog Question--Impossible?

I have a verilog file Intensifier.v. In it is a module with the following port list: module Intensifier ( clk, _reset, intensifierInput, intensifierOutpu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

--- Quote Start ---

I really appreciate people helping each other out. So many folks seem to use the Internet for the purpose of putting others down.

--- Quote End ---

Simple Concept : If we know something,we say otherwise we subscribe that thread. ;)

Pleased to help you.