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Altera_Forum
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13 years ago

Simple Verilog Question--Impossible?

I have a verilog file Intensifier.v. In it is a module with the following port list: module Intensifier ( clk, _reset, intensifierInput, intensifierOutpu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi Matthew,

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Thank you Dave and Supal.

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You're welcome.

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I really appreciate people helping each other out. So many folks seem to use the Internet for the purpose of putting others down.

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This forum has managed to stay quite civil :)

Cheers,

Dave