Simple Verilog Question--Impossible?

Thank you Dave and Supal. You were both on the right track. Supal, your solution was almost perfect, but you forgot a block name. I added this in my final code, shown below, as "INSTANTIATE_INTENSIFIERS".

I really appreciate people helping each other out. So many folks seem to use the Internet for the purpose of putting others down.

Matthew

module Test1 (

//inputs

clk,

_reset,

testIn,

//outputs

testOut

);

input clk;

input _reset;

input [1023:0]testIn;

output [1023:0]testOut;

wire [1023:0]testOutWire;

assign testOut = testOutWire;

genvar i;

generate

for ( i=0; i<1024; i=i+1 ) begin:INSTANTIATE_INTENSIFIERS

Intensifier intensifier (

.clk ( clk ),

._reset ( _reset ),

.intensifierInput ( testIn ),

.intensifieroutput ( testoutwire )

);

end

endgenerate

endmodule