simple SPI on MAX V - what's wrong here?

RTL and gate level schematics are just a logic visualization, if there's a fault I won't overrate it.

I think it's just a misleading display. Similarly the gate level schematic for MAX V misses the feedback signal inversion, but if you go to the resource property editor, it's finally shown.

I'm not working with MAX II/V in any active design now and can't check the operation of this simple circuit in actual hardware. I remember that Quartus synthesis had some problems with classic CPLD like MAX3000, but MAX II/V uses essentially Cyclone alike FPGA logic elements and should be synthesized similarly.

There's a certain chance of a bug related to MAX V in newer Quartus versions.

I suggest to advance to useful SPI logic circuits and check if the problems stay.

Timing constraints don't affect logic implementation in the first order.