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Altera_Forum
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8 years ago

simple SPI on MAX V - what's wrong here?

Hi, in a project I want to use MAX V (precisely: 5M40ZE64I5N) operating as a slave on SPI bus, so I've started to prepare a very simple module for communication over SPI bus. My device uses 5 l...
Altera_Forum's avatar
Altera_Forum
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8 years ago

The clock is shown on the oscillogram in the first post, it looks good to me. I've measured slopes of the edges, the transitions occur in less than 100ns.

Yes, ncs and nrst are driven correctly - I've checked that.

I've also tried to provide a create_clock constraint in SDC file, but that didn't help.

However with different timings, the output could display also other values, but 10101010 only appeared incidentally.

Is it possible that I get synthesized something else instead of the flip-flop? How to check that?