Hi,
While doing this I am getting the below mentioned error.
-> Top level modules:
tb_top
End time: 11:47:01 on Jan 21,2022, Elapsed time: 0:00:00
Errors: 0, Warnings: 0
[exec] elab
vsim -t fs -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fourteennm_ver -L fourteennm_hssi_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fourteennm -L fourteennm_hssi -L fifo_1910 -L fifo1 -L fifo2_1910 -L fifo2 tb_top
Start time: 11:47:01 on Jan 21,2022 # ** Note: (vsim-3812) Design is being optimized...
** Error: D:/FPGATEAM/Murali/RPU/questa_practice/fifo_ex_stote/fifo_fifo2_sim_181_project/fifo1/synth/fifo1.v(19): Module 'fifo1_fifo_1910_lpo4uxi' is not defined. # For instance 'fifo_0' at path 'tb_top.uut_inst.u0'
** Error: D:/FPGATEAM/Murali/RPU/questa_practice/fifo_ex_stote/fifo_fifo2_sim_181_project/fifo2/synth/fifo2.v(29): Module 'fifo2_fifo2_1910_lohbzay' is not defined.
For instance 'fifo2_0' at path 'tb_top.uut_inst.u1'
Optimization failed
** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=0.
Error loading design
End time: 11:47:02 on Jan 21,2022, Elapsed time: 0:00:01
Errors: 2, Warnings: 0
cannot find item *i_data*
Occasional Contributor
