Signaltap problem with Stratix 10 Production Kit

I have created a very simple project in Quartus 18.0 for a stratix 10 development kit. The project uses a 100MHz clock to drive a counter, which counts from 0 to 99. I have added a signaltap instance which uses the 100MHz clock and observes the counter.

During compilation of the project, I get these warnings:

Warning(332060): Node: altera_reserved_tck was determined to be a clock but was found without an associated clock assignment. 
 
 
This warning appears six times: (For each temperature/speed model I assume)
 
 
Warning(332182): No path is found satisfying assignment "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_in_reg[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_out[*]}] 1.000 ". This assignment will be ignored. 

The compilation completes with no errors, so I go to signaltap to program the board. After choosing the correct device and .sof file, I click the program button.

During programming, this message appears in the System tab of the Quartus message pane:

Info(209060): Started Programmer operation at Fri Feb 1 15:23:52 2019 
 
Info(18942): Configuring device index 1 
 
Info(18943): Configuration succeeded at device index 1 
 
Info(209011): Successfully performed operation(s) 
 
Info(209061): Ended Programmer operation at Fri Feb 1 15:23:53 2019 

Despite this seemingly successful programming, the signaltap status bar still says 'Program the device to continue' with a red background. If I try to acquire data, This message appears in the System tab of Quartus:

Error(261005): Can't find the instance. Download a design with SRAM Object File containing this instance. 

I believe the issue has something to do with the warning above (No path is found satisfying assignment....). I tried investigating this using the Timing Analyser.

I opened Timing analyser, and ran the 'Create Timing Netlist' command. After that I ran

   get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_in_reg[*]}

Which did not produce any errors. Somehow this register is not defined during programming, but when I run 'create timing netlist'.

In fact, running the whole command

   set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_in_reg[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_out[*]}] 1.000 

produces no errors.

Why would this cause an error at compile time, but not when running the timing analser?

I have tried this in both Quartus 18.0 and 18.1. In 18.1, I get this error when I try to program the board:

Info(209060): Started Programmer operation at Fri Feb 1 15:49:42 2019 
 
Info(18942): Configuring device index 1 
 
Error(18948): Error message received from device: Detected hardware access error. There is a failure in accessing external hardware. (Subcode 0x0032, Info 0x00000000, Location 0x0000C400) 
 
Error(20072): A PMBUS error has occurred during configuration. Potential errors: Incorrect VID setting in Quartus Project. The target device fails to communicate to smart regulator or PMBUS Master on board. 
 
Info(209028): Operation canceled 
 
Info(209061): Ended Programmer operation at Fri Feb 1 15:49:44 2019 

I suspect my power settings and VID are incorrect, but I'm not sure why this would be a problem in Quartus 18.1, but not 18.0.

Any help would be very appreciated

Thanks,

-Sam