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SDe_J
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Signaltap problem with Stratix 10 Production Kit

I have created a very simple project in Quartus 18.0 for a stratix 10 development kit. The project uses a 100MHz clock to drive a counter, which counts from 0 to 99. I have added a signaltap instance...
SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi sstrell,

I have ensured that the signaltap file is enabled (if I disable it, I don't get the compile warnings about signaltap that I posted). I have not added any timing constraints to the design, but those warnings show up anyway.

I got the device I'm using from an example project for the stratix 10. The precompiled .sof file for that project downloads to the board correctly, so I'm reasonably certain that I've got the device correct.

-Sam