Honored Contributor
Honored Contributor1. The number of samples can be set to a power of two up to 128k, if you have sufficient on-chip memory available. You did neither tell the involved FPGA type nor the signal width, so we can't know the maximum setting. But SignalTap informs about the RAM utilisation, so you can set it to the maximum possible value.
2. 10ms at 40 MHz would mean 400k samples. This sample size isn't supported by SignalTap. Besides using a slower clock, you can also enable a storage qualifier to reduce the sample frequency. 3. A continuously sustained acquisition at a high sampling frequency is basically impossible due to the limited JTAG throughput. Even at slower speeds, it would require an interleaved sampling and JTAG transmission scheme, not supported by SignalTap as far as I know.
