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Altera_Forum's avatar
Altera_Forum
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14 years ago

SignalTap II questions

Hi, I have 2 questions regarding SignalTap: 1. Sometimes I see 2 active states in a state machine - how is it possible? I assume that it means that there is a bug, what kind of bug can cause tha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I was able to make things better by reducing the frequency of the main clock (it is much faster then the input signals that are being sampled). I can still see the problem sometimes though.

I'm working on properly constraining the design (I'm not an expert). My basic clock is much faster than the input signals and the device utilization is very low, isn't that enough to put me on the safe side of the timing issues?