Forum Discussion
Altera_Forum
Honored Contributor
8 years agoRun a timing report in TimeQuest for the failing constraint(s) and in the report look at the launching and latching clocks. If they are not the same then that's your problem. If these are false paths then you can tell TimeQuest to ignore them using the set_clock_groups command. That's a more general-purpose way to ignore the paths than set_false_path or set_max_delay. But if you are getting sampling errors in SignalTap then the paths are really not false and you're violating a very basic design rule. Usually the right way to handle this is to have a separate SignalTap instance for each clock domain, all in the same .stp file. Then you can select one at a time to trigger, or you can add cross triggering if you need it.