SignalTap fails timing often

What I meant by that is that I get the timing violations between my nodes that I add in the logic analyser manually, and the registers that are generated to store my signals(acq_data_in_reg[*]). I cannot prepare for these kinds of violations by setting the maximum delay of the signal getting there, as I do not know the required delay before compilation.

If I have a larger design, checking each and every one of these violations and applying the max delay to them can take a considerably large amount of time, and is generally unpleasant if I have to do this every time I peek somewhere else in my design.

I do see the violations in the TimeQuest analyzer, I am just searching for a way to generally prevent them, when peeking to various places in my design. I hope I got my message through better now :)