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Altera_Forum's avatar
Altera_Forum
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10 years ago

Signal Tap II register missing verilog

Hello Everybody,

I would like to observe an internal register (written in verilog) in signal tap II logic analyser. but I couldn't find it there. I even used preserved option like

reg reg1 /* synthesis preserve = 1 */;

but it also doesn't help.

when I use noprune like

(* noprune *) reg reg1;

then I have the error as

can't resolve multiple drive for .....bla bla bla.

Is there any solution for this?

Regards

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I use the following

    in verilog:

    to save a wire:

    wire net1 /* synthesis keep */ ;

    to save reg:

    reg reg1 /* synthesis preserve */;

    if the register has no fanout you have to use

    reg reg1 /*synthesis noprune */;

    There has only been 1 time that I couldn't get the signal to preserve. I used assignment editor in Quartus to find the signal and preserve it there.

    9.9 out of 10 times the first method works