Honored Contributor
Honored ContributorI have heard of people running into this and it's typically caused by a timing bug in the hardware design. When you add signaltap you are adding resources to the design, and as a result changing the place and route of the logic which will cause timing changes. If your statemachine takes in inputs from the I/O then make sure those paths are constrained because Timequest cannot analyze those paths without constraints since it doesn't know anything about your board timing without them.
Without constraints what could happen is an input flip flop fails timing but when you add signaltap that FF gets pulled further into the FPGA fabric and ends up capturing data one cycle later. So this would be a valid timing failure that Timequest may not catch if the I/O are not constrained.
