Signal Processing

The simplest thing to do is to do fft on the signal from ADC.

To avoid complex software work for pc interfacing you can capture fft output in signaltap or memory editor and then use a tool e.g. matlab to display result.

You can also do fft on PC if signal slow enough. In this case you only need to capture ADC data directly in signaltap or memory editor.

You will need to enter your frequency axis based on sampling rate of ADC.

Are you building a 'receiver' or 'spectrum analyzer'? A receiver implies you have some sort of signal you are expecting to receive, whereas a spectrum analyzer is used to determine the power vs frequency in the signal being received.

You can check that your ADC works by capturing a block of samples, and then transferring those samples to a PC for analysis. However, you will not get very good signal-to-noise, since you will have such a low processing rate.

You can perform the operations directly on the FPGA. There are two forms of spectrum analysis commonly implemented that achieve maximum SNR; auto-correlation via lag correlation and a polyphase filterbank (basically a filter followed by an FFT). If SNR is not an issue, then you can use an NCO to demodulate your signal, a low-pass filter, and a power detector (multiplier), and sweep the NCO across the input bandwidth.

What bandwidth are you trying to sample? What FPGA are you planning on using? What types of signals are you hoping to receive? How many bits are your ADCs.

Cheers,

Dave

Hi Dave, thanks for all.

My problem is: I have a frequency range 100 KHz to 3 GHz and I have to detect all signals between that frequency range, for example (AM, FM, GSM, Bluetooh...etc). I need to choice a ADC and implement the signal processing in FPGA. I don't know which ADC I can use. The maximum bandwith that I have to try to sample is 20 MHz, But I don't know how many bits my ADC must have.

How can you sample a 3GHz signal with 20Mhz ADC?

There's something wrong in your specifications.

If you want to the 3GHz signal you have to sample at more than 6 GHz.

For the numebr of bits, well, if money is not a problem the highest the better.

You can always neglect the LSBs later.

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Hi Dave, thanks for all.

My problem is: I have a frequency range 100 KHz to 3 GHz and I have to detect all signals between that frequency range, for example (AM, FM, GSM, Bluetooh...etc). I need to choice a ADC and implement the signal processing in FPGA. I don't know which ADC I can use. The maximum bandwith that I have to try to sample is 20 MHz, But I don't know how many bits my ADC must have.

--- Quote End ---

You still have not specified what you want to do with the signals.

By 'detect' do you mean demodulate, or just 'detect' power?

The number of bits required from your ADC will depend on what type of signal processing you want to perform. However, a 16-bit 100MHz ADC will likely do anything you want. There are Altera HSMC cards with that feature (Terasic), and some of the Altera DSP kits have 100MHz ADCs.

Are you planning on buying a commercial demodulator? Building a demodulator that takes 3GHz down to DC is a non-trivial task. You will likely need different types of analog front-ends, and switch between them, eg. op-amp based designs from DC to ~100MHz, and RF amplifiers above that.

Of course, you could sample the signal directly, but you would need an ADC with an analog input bandwidth of over 3GHz. National Semiconductor and e2v have GHz clock rate parts, eg.

http://www.e2v.com/products-and-services/hi-rel-semiconductor-solutions/broadband-data-converters/datasheets/

You might be able to find a manufacturer with one of these ADCs on an Altera board, eg. Bittware

http://www.bittware.com/products/hardware/prod_desc.cfm?prodshrtname=3fad-s43x

Depends whether you're looking to build or buy really.

Cheers,

Dave

Hi Dave,

Thanks for your tip.

You asked me what I will do with the signal, detect and demodulate or just detect the power.

In my case I want just detect the power, not demodulate.

thanks for all

If the ADC output represents a bandlimited signal, calculating the variance will give the total signal power. It's a rather simple algorithm.

The overall problem is however missing many specification details. The questions you are asking can't be answered without a full specification, Furthermore, the way you are asking suggests that you are far from understanding the problem complexity.

Hi people,

I have all details, but which details you want to know.

thanks