signal power estimation

Thank you kaz.. I'm on it..

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
ENTITY rms_estimator IS
    GENERIC (ACCBIT : INTEGER:=10);
    PORT( squared_abs : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
            clk , clr : IN STD_LOGIC;
            squared_rms: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
            ready : out STD_LOGIC;
END ENTITY rms_estimator;
ARCHITECTURE logic OF rms_estimator IS
signal sum : STD_LOGIC_VECTOR(ACCBIT+31 downto 0):=(OTHERS =>'0');
signal i : STD_LOGIC_VECTOR(ACCBIT downto 0):=(OTHERS =>'0');
BEGIN
PROCESS(clk,clr)
    
   BEGIN
        IF(clr = '1') THEN
            squared_rms<=(OTHERS =>'0');
            sum<=(OTHERS =>'0');
            ready<='0';
            i<=(OTHERS =>'0');
        ELSIF rising_edge(clk) THEN
            if (i=2**ACCBIT) then
               squared_rms<=std_logic_vector(sum(ACCBIT+31 downto ACCBIT));
               ready<='1';
            else
                sum<=  sum + unsigned(pad & squared_abs);
                i<=i+1;
                ready<='0';
                squared_rms<=(others=>'0');
            end if;
        END IF;
    END PROCESS;
END ARCHITECTURE logic;