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Altera_Forum
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16 years ago

Signal Integrity Issue

Hi, I am having a small issue with a stratix II device regarding a 10MHz I am using in an SPI Interface. Basically I have a 10MHz clock entering the FPGA and it seems with a small amount of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hi,

maybe I'm wrong, but in the first picture the timescale is 20ns/div. So it looks like that you are running at 50 MHz ????

Kind regards

GPK

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This was due to an error when I saved the screenshot. I initially saved it some strange format that I couldn´t open on the PC so I then went back, opened the same file and resaved it as a jpeg. It seemed to have taken the current time/div setting, which wasn´t the same as when the original was captured.

It´s definately a 10MHz signal. Sorry for the confusion