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Altera_Forum
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17 years ago

Signal has no source

Hi All! When i compile the following code: (Quartus) entity ISA is port --from ISA to CPU (AEN_IN,IOR_IN,IOW_IN :inout std_logic; ADDR_IN : inout std_logic_vector(10 downto 0); ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks for the valuable information.

Actually DATA_IN is bidirectional, i read from and write to it.