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lounug's avatar
lounug
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Signal falsely changes to '1' after clock starts

Hi, I got a very rare case that I have never seen before after years developing Intel FPGA Design and verifying the design using SignalTap. A std_logic signal that has initial value of '0' and...
  • FvM's avatar
    FvM
    3 years ago
    You should definitely try a reset synchronizer. For implementation, see paragraph recommended design practice - asynchronous reset in Quartus manual.
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey



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