Shifted clock signal when connecting to FPGA (cyclone iii)

I've tried using the megawizard now but I am getting the same results. In Quartus II (web version 11.0) I clicked Tools->MegaWizard Plug-In Manager. I followed along with one of the examples in the ug_altpll.pdf file to do something similar for a single clock in and single clock out line (I opted out to not use a locked pin or feedback 'fbin' pin). I made necessary changes to use Cyclone III device instead of Stratix device as used in the example. When I completed the wizard, I generated a VHDL file which I used for a project with 2 pins. I assigned the input 'clkin0' port to input pin 149 of my device (DIFFCLK_3n) and output 'clk' port to output pin 240 of my device (PLL3_CLKOUTp).

I compiled the design, with no errors and no critical warnings. I then powered up and programmed my fpga on my board and then turned on my oscillator signal applied to pin 149. Scoping the output I see the same results as what I had seen with just regular user I/O pins (Basically the output is a high 3.3V signal with lots of noise). So it seems like the triggering is still not happening on rise and fall of my clock signal but somehow the noise is passing through.

In the assignment editor I've chosen 3.3V LVCMOS as my logic levels. This is consistent with my VCCI/O however perhaps I should chose 2.5V for my PLLs as I know 2.5V is used to power the PLL lines through a choke/ferrite bead (VCCA1 - VCCA4 is 2.5V, VCCD_PLL1 - VCCD_PLL4 is 1.2V).

Is there a way to select the 'optional pin function' for the pins I am using? When looking at the pinout information for Cyclone III devices there is a column for Pin Name/Function and then another column for Optional Function(s) so perhaps I need to make that selection somewhere in the assignment editor or somewhere else?

I hope I was able to explain myself clearly. Any suggestions are welcome! Thanks.

Edit1 3/4/2014: I forgot to mention also, my clock source looks like an AC waveform (fairly clean looking but not square wave at all). Is that a problem for triggering high and low levels? It ranges from 0-2.3V which according the the cyclone iii spec should trigger the Vih and Vil for 3.3V LVCMOS. But perhaps i'm missing something here. I should maybe use TTL?