Shift register with asynchronous parallel load : Latch warning

Hello,

Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
    Warning (13310): Register "tmp" is converted into an equivalent circuit using register "tmp~_emulated" and latch "tmp~latch"
   ...
    Warning (13310): Register "tmp" is converted into an equivalent circuit using register "tmp~_emulated" and latch "tmp~latch"

library ieee;
use ieee.std_logic_1164.all;
entity shift_reg is  
port
(
    C, ALOAD : in std_logic :='0';     
    D            : in std_logic_vector(15 downto 0):= (others =>'0');       
    SO          : out std_logic:='0'
);
end shift_reg;
architecture archi of shift_reg is  
signal tmp     : std_logic_vector(16 downto 0) REGISTER := "00000000000000000";
signal adata : std_logic_vector(16 downto 0) REGISTER := (others=>'0');
signal count : integer :=0;
begin 
    
    process (C,ALOAD,adata) is
    begin
    if ALOAD='1' then
    tmp <=adata;
    elsif (C'event and C='1') then
        If Count<16 then
        tmp <= tmp(15 downto 0) & '0';
        end if;
    end if;
    end process;
     
    process(C, ALOAD)
    begin
    if (ALOAD = '1') then
    count <= 0;
    elsif (C'event and C='1') then
    count <= count + 1;
    end if;
    end process;
    
adata <= '0' & D;
SO     <= tmp(16);
end archi;