SGDMA data transfer question.

Bursting can potentially have two negative effects:

1) In SOPC Builder burst adaptation was inefficient, especially with small burst sizes. The burst adapter would always have a single dead cycle at the start of a burst so if you used a burst count of 2 you are talking at best 3 clock cycles per burst. Qsys doesn't have this limitation, it's just an SOPC Builder thing.

2) With DMAs (not sure about the one you are using) the DMA engine typically waits for a full burst to be read and buffered before issuing out a burst write. The bigger the burst length the more time the write master has to wait before issuing the burst.

Assuming you are using a modern SDRAM controller from Altera, you can change the local burst length of the slave port. I typically turn that down to 1 and let the controller combine sequential accesses into a single offchip burst. Then you don't need to worry about enabling bursting in the master logic or any burst adapters that might be created as a result.