SGDMA data transfer question.

On chip memory ought to be able to read/write a location every clock - although the read data isn't available until the following clock cycle. That certainly happens when for the Nios 'tightly coupled data memory'. It would require Avalon burst accesses.

Were you measuring SDRAM reads or writes? they will behave differently.

My experiments suggest that writes are 'posted' (ie acked immediately) unless the logic is busy. The first write will then be actioned, subsequent writes are held in a 'line buffer' (probably 32 bytes, maybe 64) provided they address adjacent locations. When the underlying write completes, the contents (if any) of the line buffer are written out. So writes only stall if they address a location that cann't be buffered.

Reads will read an entire line buffer - then return the requested location. Further reads for nearby addresses return data from the buffer. Fully random reads are about 16 clocks.