SGDMA data transfer question.

The SDRAM is a synchronize burst device, the transferring speed of this SGDMA method is at the same speed of the driving clock of the sdram controller,

your 370MB value must be divided by 4, approximately 92.5MHz, slightly less than 100MHz, for the row and column address latch cycle and the the read

latency cycle, in fact, the SOPC system can implement the multi- page (256 read or write cycle) transfer, for this reason, it is recommended to enable

the page mode of the SGDMA to get the highest efficency.

The following gave you the reason of the SRAM speed, if you must kown that the PLD devices are unsuitable for the asynchronized memory interface, the

SOPC system implented the random accessing to the SRAM based on the clock of the 1/3 speed of the SRAM controller, if you use this 100MHz, it only 33MHz

be avaliable, well, apparently you only get the speed of 25MHz, I think you can explain this well (you can scope this through the signaltap II tool), ...

in fact, you can get the maximum random access speed up to 100MHz if the asynchronize SRAM is a 10ns devices, at least up to 80MHz, ... it realy a waste

to integrate the asynchronize SRAM on SOPC system, ...