SGDMA data transfer question.

I assume by BRAM you mean on-chip memory. On-chip RAM is both high speed and low latency so you can't find a more efficient memory-to-memory transfers speed using an FPGA than between two on-chip memories. For example if I moved 50000 words of data between two independent on-chip memories, and assuming the DMA is the only thing accesses them you can expect a transfer time of approximately:

2 cycles (on-chip RAM latency) + ~ 4 cycles (latency through the DMA) + 50000

With an SDRAM that equation becomes (assuming two SDRAMs are involved):

12+ cycles (SDRAM latency) + ~ 4 cycles (latency through the DMA) + (50000 * ~0.95 (SDRAM has addressing and low level command overhead))

So if you replace one of the on-chip memories with SDRAM, it's the SDRAM that will be the limiting factor.