Altera_Forum
Honored Contributor
14 years agoSFL for loading EPCS
Hello,
I have several questions before designing a new board with cyclone device and I'll be happy if you could help with this issue. I would like to configure cyclone III EPCS via JTAG, there is an option to do that via SFL. Couldn’t understand exactly how to use this option. I want to make sure I understood it correctly. 1. Case I want to configure EPC via JTAG interface and If resetting the FPGA is not an issue for me during the EPCS programming all I need is to convert .sof to .jic file in quartus II software, set the EPCS type and program .jic file via quartus programmer. Am I right????? All the process is automatic. 2. Case I want to allow EPCS programming without resetting my design I will use SFL megafunction and instantiate the SFL image into my VHDL design. The SFL megafunction in vhdl has I/Os (dclk_in, ncso_in,asdo_in,noe_in,asmi_access_granted, data0_out,asmi_access_request). Where sould I connect these I/Os ???? Where should I place SFL megafunction? 3. Can I use 1,2 options with FTDI-FT2232H's JTAG interface, Instead of USB Blaster download cable?