Honored Contributor
Honored ContributorRysc,
I can't find any documentation on set_data_delay in the quartus 17 tools or online documentation. Do you know of a source for that documentation? I'm trying to find a good reference for constraining clock domain crossing paths. From what I understand, set_false_paths between clock domains is not the preferred way. You are supposed to use a combination of set_max_delay, set_min_delay, set_max_skew, and set_net_delay commands. In Xilinx, the way I've seen CDC paths is to use a set_max_delay -datapath_only constraint. But, Altera doesn't have a -datapath_only switch for it's set_max_delay constraint. So, I assume that in order for the cdc paths to be constrained correctly, you have to do something to 'ignore' the clock skew. This is why I was interested when I saw your post about set_data_delay - and was wondering if this was the Altera equivalent of the Xilinx set_max_delay -datapath_only constraint. Seems like this would be a much simpler way to constrain cdc paths, than to have to do the set_max_delay, set_min_delay, set_max_skew, and set_net_delay constraints for ever cdc. I'm assuming this thread best describes the way to constrain cdc paths (although I don't have a special 'map_cdc' module that I use in my design - was hoping I could just specify all paths between CLKA and CLKB): https://alteraforum.com/forum/showthread.php?t=55835
