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Honored Contributor
Honored Contributorset_max_delay value in TimeQuest
Hi I should constaraint "set_max_delay -from reg_A to reg_B". In my case , My circuit run 200MHz(refer to wave picutre). I estimated register to register max delay value was 5.0ns . but Time...
Altera_ForumHonored Contributor
Honored ContributorDear sanmao
>So you should optimize the combinatorial logic in your circuit, >reduce the depth of the combinatorial logic or add pipeline registers in between. I thought I can constraint "set_max_delay -from reg_A to reg_B 5.40ns". is it OK? Becouse TimeQuest required 5.741ns in this path. It means, Can reg_b latch after Latch_edge in this pass ?
