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JJin01's avatar
JJin01
Icon for New Contributor rankNew Contributor
7 years ago

set_clock_group question..plz help me

There are clka and clkb (asynchronous source), divclka is made from clka, and there is clock mux .. i contrainted them like below, create_clock -name { clka } -period 10.0 [get_ports{ clk...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

The OP doesn't need set_false_path constraints if they use set_clock_groups. That's the whole point and one of the main advantages of set_clock_groups!

#iwork4intel