serious problems about FIFO simulation

I implemented altera FIFO in my design and passed the functional simulation in Altera-modelsim 6.5e.

But I failed in the timing simulation,both writing and reading FIFO behavior.

On the basis of phenomenon,I concluded the reason:

In the testbench where clk is generated,I implemented the writing FIFO behavior like this:

always @(posedge clk)begin

....

if(wrreq)

fifo_data_in <= ***;

end

the data port is updated immediately,but in my design,it will delayed for the fitting results,so,probably,the setup or hold time failed!

My question is:How can I compensate the delayed time,and simulate FIFO successfully???

Thank you for your help!