Serializing Avalon-ST over XCVR for FPGA-to-FPGA Transmission

You'll want to use a mode that incorporates the 8/10B encoder. This makes recovering bytes out of the serial data stream trivial, and supports mismatched data rates through the use of IDLE codes.

I have not used it, but I am pretty sure the SerialLite core is for light-weight chip-to-chip communications. Xilinx have a similar protocol called Aurora. I don't know how compatible these two protocols are. Perhaps someone who has used them can comment.

You should "do the math" to determine what sort of bit-rate you require, what sort of lane rate you think your PCB can handle, and hence how many SERDES lanes you will need.

Cheers,

Dave