Hi,
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Quote:
I was thinking here about using one module to do that , use if statement to define the values , and then send those values with record type like my_record.to_count to other modules. If i needed to change the if staement - i could to that in one file , not all the submodules.
If your DIP switch settings are used to define some operation, then you can use an if-statement, or case-statement.
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Yes that's what i wanted to do - but i wasn't too specific. I meant that i could route my std_logic bits to the let's say config_module, and in this config module to analize those bits - use case or if statements, and send configuration info to the rest of the modules - like number of counts, upper level, or stuff like that.
I'm thinking that with this approach, i wouldnt have to put those if or case statements in every SUBMODULE - my config_module would do that and give the configuration info to the rest of the modules.
It also gives me lower number of ports in my modules, and it would be easy to add more configuration info without the need of modificating all if case statements of all other modules (and also adding signals).
And my real question here was that will there be no problems after synthesis with using records to do that? In configuration record i would have std_logic and unsigned. And if this approach is correct?
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Please give me your opinion Dave about:
2) I have to send for example 8 (it could be changed with those configuration) vectors - each 24 bit long.
Those are the part of 32 bits read from my fifo.
I want to stream them out to 4 pins with I2S. (2 vectors for one pin)
I was thinking about using next state machine to control that (there's also one main state machine that controls other stuff). And here's the port of my i2s_Transmitter:
entity i2s_transmitter is
port(
clk_in : in std_logic; -- same as the main state machine
bitclk_in : in std_logic;
wordclk_in : in std_logic;
strobe : in std_logic;
data_in : in std_logic_vector(23 downto 0);
transmitter_busy_flag : out std_logic;
i2s_out : out std_logic_vector(3 downto 0)
);
end i2s_transmitter;
My idea was that my main state machine would latch those eight 24 bit vectors with strobe flag. I2s transmitter would count the latched data with strobe flag - and according to nr of vector , it would be put in shift registers like:
signal channel_12_shift_reg : std_logic_vector(47 downto 0) := (others => '0');
signal channel_34_shift_reg : std_logic_vector(47 downto 0) := (others => '0');
signal channel_56_shift_reg : std_logic_vector(47 downto 0) := (others => '0');
signal channel_78_shift_reg : std_logic_vector(47 downto 0) := (others => '0');
-- and after begin
channel_counter_inc : process(clk_in, strobe) is
variable channel_cnt : integer range 0 to 8 := 0;
begin
if rising_edge(fsm_clk_in) then
if channel_cnt = 8 then
transmitter_busy_flag <= '1';
channel_cnt := 0;
elsif strobe = '1' then
channel_cnt := channel_cnt + 1;
end if;
case channel_cnt is
when 1 =>
channel_12_shift_reg(47 downto 24) <= data_in;
when 2 =>
channel_12_shift_reg(23 downto 0) <= data_in;
when 3 =>
channel_34_shift_reg(47 downto 24) <= data_in;
when 4 =>
channel_34_shift_reg(23 downto 0) <= data_in;
when 5 =>
channel_56_shift_reg(47 downto 24) <= data_in;
when 6 =>
channel_56_shift_reg(23 downto 0) <= data_in;
when 7 =>
channel_78_shift_reg(47 downto 24) <= data_in;
when 8 =>
channel_78_shift_reg(23 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end process;
After all channels are latched into the shift_registers , the transmitter module sends transmitter_busy_flag. Next i was thinking about using 1port ram - with 4 bits input, output.
input would be smth like:
ram_data_in <= channel_12_shift_reg(47) & channel_34_shift_reg(47) & channel_56_shift_reg(47) & channel_78_shift_reg(47) &
And transmitter state machine would put it with clk_in into the ram.
the output would be i2s_out : out std_logic_vector(3 downto 0) (routed in the top level entity to pins)
Then the FSM would deassert transmitter_busy_flag and start pushing the data form ram with bitclk_in, correctly after both edges of wordclk_in ( with i2s specification - after one bit clock etc. )
I suppose that it sucks :) so thanks for any advice.
best regards
Honored Contributor
