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Altera_Forum's avatar
Altera_Forum
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13 years ago

Serial data from shift register to FIFO

Hi,

let's assume conditions:

Receive domain:

Data clock : 125 MHz

Data encoded with with 5b/4b method

Data frame contains 32 * 64 bits (4bits before encoding - 40 * 64 bits in 5bit version)

Frame frequency is 44 kHz

The begin of the frame is synchronized with following bits "11000"

So first i have to detect the beginning of the frame - i use for this 15 bit shift register. Serial data goes into the shift registers , and sync is asserted when the most significant 10 bits are 1100011000 and the least significant are different from 11000. Shift register is clocked with 125 MHz.

My object is to:

After getting sync flag, i need to decode 5 lsb bits of shift register into 4 bits. And put them into the FIFO.

After decoding data from 5 bit to 4 bit i get 25 MHz clock to drive the wrclk of the fifo.

So my question is ->

How to correclty get this 5 bits (then 4 bits) into the fifo ?

I assume that this 25 MHz clock is derived directly from this 125 MHz clock , so the are synchronized.

I should also assert correctly wrreq signal in fifo - and use a counter to write only these 32 * 64 bits and nothing else.

wrreq must be asserted somehow before the rising edge of wrclk (falling edge) ? What if i assert it in the rising edge? Will data be put into the fifo, or on the next cycle? Or something wrong will happen ?

I suppose that i should use a synchronizer for the sync flag in 125 Mhz- but don't know how to do it - it will give some delay to the sync in 25 MHz domain. I will lose then the actual data from the shift register (it will be shifted with 125Mhz clocks before i will be able to correctly read those 5 bits and put them into 25 Mhz clock domain) ?

Sorry for the mess, thanks for any suggestions and help

best regards

madness

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi, everything works fine for now.

    However i need your expertise on my new problems : )

    I'm working on NRZI transmitter -> when i deserialize my data to the 32 bits, i want now to encode them into 40 bits (4b/5b encoding) and put all these 40 bit 64 channels into FIFO, and when the FIFO contains two 64 channel frames - > to start transmitting them from the device. FIFO has 40 bit data in and 40 bit data out. I tried to do smth like that:

    https://sites.google.com/site/pauldab/home/data1.jpg

    Detect the rising edge of my world clock using 125 MHz clock:

    https://sites.google.com/site/pauldab/home/data2.jpg

    It's used for reseting counters:

    --- Quote Start ---

    process(fsm_clock)

    begin

    if rising_edge(fsm_clock) then

    wck_edge_detector(0) <= PIN_wck;

    wck_edge_detector(1) <= wck_edge_detector(0);

    end if;

    end process;

    -- and in other processes - clocks processes

    ...

    if wck_edge_detector = "10" then

    ...

    --- Quote End ---

    I have 2 counters that i currently use , tx_sout_counter -> this is the counter that counts form 0 to 39. When the counter is equal to 0 it generates the fifo rdreq flag so the data should appear on the line. (One bit of the shift register is connected to the nrzi output -> a module that transmit using XOR NRZI bit stream)

    When tx_sout_counter is other that 0 , the shift register is shifted.

    The first image once again:

    https://sites.google.com/site/pauldab/home/data1.jpg

    PIN_wck_out - the name here is irrelevant -> i just had to assaign signal that is 1 when tx_ch_counter is 0 to 63. There's when with tx_sout_counter i have to read data from FIFO , and then shift them. When the flag is 0 i have to transmit 10 bit synchronization bits:

    B"1100010001"

    However my problem here is that:

    When i transmit my data , after data i have to transmit synchronization bits until the rising edge od word clock is detected. But i have to transmit full 10 bits , i can't just transmit 3 of them when rising edge was detected. Cause then in my receiver wrong data would be synchronized and received.

    So my transmitter would be correct with word clock +- 10 synchrnization bits. I know that it deosn't matter and it should be like that.

    But problem with my counters is that, when i'm at the end of word clock, and i transmit 2 bits of synchronization, then the rising edge is detected, all the counters are set to 0, and the actual data is being transmitted (i lose those next synchronziation bits). I really don't know how to do it to send full 10 bits.

    Perhaps i should somehow transmit 10 bits-> then check if the rising edge occured, if yes start transmitting data, if not transmit next 10 bits and then check again if the world clock rising edge occured.

    I don't even know for now if this method with reading from fifo, and serializaing it that way will give me good results.

    What would be the easiest and nicest way to do it ? : )

    best regards