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Hi madness,
Ignore the FIFO to start with.
Create a design clocked at 125MHz, which contains the shift-register, your synchronization logic, and a counter. Use the counter to generate the output data valid/enable pulse at the 25MHz output data rate, i.e., every 5th input bit period.
Once you get that working, writing to a FIFO is simple, you connect the enable bit to the write-enable on the FIFO. If you wanted to use a dual-clocked FIFO, you could use the 125MHz as the reference to a PLL and have that PLL generate a 25MHz clock. That 25MHz clock could then be used on the other port of the FIFO. However, you could probably also leave your design running at 125MHz and simply use the data valid indicator along with the data.
Create a Modelsim simulation of this design, and feed it a known serial bit stream and confirm that it decodes correctly.
Cheers,
Dave
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hi,dave
what't the difference between the 25Mhz clock generated by the PLL that generates 125Mhz or another PLL ?that means the compiler will treat clocks from different PLLS as asynchronous clocks ?even if two PLL's inclk are from the same clock source.or we use command "set_false_paths" to solve this?:)
thanks,
yang
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