Forum Discussion
New ContributorSerdes Ref clk input circuit
Hi,
Yes, Cyclone V receiver buffer does has internal on-chip biasing circuitry but we can't expose the internal circuit design as it's Intel proprietary design info.
However, we do have user guide doc that explained on available feature in receiver buffer. You can checkout chapter "Recevier PMA datapath" (Page 20) in below user guide link
Thanks.
Regards,
dlim
Regular ContributorHI,
You can refer to Cyclone V datasheet (table 21, page 25) for the supported IO standard for transceiver refclk pin.
I can see some of the IO standard that you mentioned but I don't see HSTL is a supported IO standard in the list. Pls switch to use supported IO standard as mentioned in Cyclone V datasheet.
Thanks.
Regards,
dlim
TRoeDeshi,
I don't understand how your IC can take either ground referenced signals or biased signals. Do you have a blocking cap inside? I was hoping for an equivalent circuit schematic if you have one. Thanks
