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HHo2's avatar
HHo2
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7 years ago

Sending packet through Stratix 10 but Linux and Wireshark can't receive.

I have implement 25g ethernet IP, and test it by sending and receiving packet between 2 of fpga 25g port, port A and port B. both of FPGA port can send and receive data, and can be confirmed by sign...
RRomano001's avatar
RRomano001
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7 years ago

Hi, sorry if it seems silly, Cabling are correct? So both FPGA I suppose have same connector and use same board, from your word it seems like packet travel just in one direction.

You have to publish more detail about otherwise it is impossible try answer similar question we cannot imagine if far from board and test bed.

Regards

  • HHo2's avatar
    HHo2
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    7 years ago

    Yes, cabling are correct.

    seems like packet travel only in one direction, FPGA can receive data from mellanox, but mellanox can't receive data from FPGA.

    So, I want to know is there anyone have project that communication between FPGA and mellanox?