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Altera_Forum's avatar
Altera_Forum
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13 years ago

Self reset to FPGA

Hi, I'm integrating an independent FPGA which doesn't have a master CPU associated with it. I need to reset the FPGA right after it enters user mode. Will using Init_done signal Anded with Co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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can you point me to the docs where they recommend reset circuitry?

if there aren't any async signals to the reset counter, there isn't any recovery/removal to worry about, is there?

interesting discussion, thanks :)

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have a look here:

http://www.altera.com/support/kdb/solutions/rd06112009_450.html

regarding reset,during POR all registers are held in reset of device then it is released. I assume this reset is applied through asynchronous port.

remember also external reliable reset is essential in real projects.