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Altera_Forum's avatar
Altera_Forum
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13 years ago

Self reset to FPGA

Hi, I'm integrating an independent FPGA which doesn't have a master CPU associated with it. I need to reset the FPGA right after it enters user mode. Will using Init_done signal Anded with Co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

can you point me to the docs where they recommend reset circuitry?

if there aren't any async signals to the reset counter, there isn't any recovery/removal to worry about, is there?

interesting discussion, thanks :)