Self reset to FPGA

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the counter can power up to 0 upon configuration. is there a reason that won't work?

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In prinsiple it should work but altera recommends external reset. I think the reason is that it may fail occasionally due to clock hitting the registers when released from chip reset right after configuration leading to violation of recovery/removal with initial zero changing to unknown value which may freeze the counter or kick it after beyond decision point that generates user reset. A large counter then means less probability of failure.