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Altera_Forum
Honored Contributor
Honored ContributorSelf reset to FPGA
Hi, I'm integrating an independent FPGA which doesn't have a master CPU associated with it. I need to reset the FPGA right after it enters user mode. Will using Init_done signal Anded with Co...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- a slightly different tactic is to drive a counter from a clock you know will be active when the FPGA is configured. run the counter for the desired length of time (count value), and reset your user logic based on this signal. this is sometimes done to wait for the input clock to stabilize before coming out of user reset --- Quote End --- But you see, the counter has got to have a reset condition. i.e it must be have a starting point but that is the problem... I have no reset condition to apply.
