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KRasm4's avatar
KRasm4
Icon for New Contributor rankNew Contributor
5 years ago

Selecting correct clock signal on Cyclone V GT DevKit

I have recently acquired the Cyclone V GT Development Board https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=843 , my first Intel board moving over from Xilinx bo...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Have you tried to simulate the design to check the functionality?

For incomplete assignment, you may check if you have set all the I/O assignments to the affected pins (pin location, I/O standard, etc). Use the Assignment Editor or the Pin Planner to add the missing I/O assignments to the affected pins.


Thanks

Best regards,

KhaiY